Home > Technology > Patents    
Patents
Download Documentation
 
Patents

From the beginning, MoSys has been a leading technological innovator, and the company's large engineering team has built an extensive patent portfolio. The company has 146 patents worldwide, representing over 500 staff-years of research and development.

Below are some examples of current MoSys patents. (Includes patents originally awarded to Atmos Corp., acquired by MoSys in 2002.)

  US Patent # Patent Description
1 5,265,047 High Density SRAM Circuit with Single-Ended Memory Cells
2 5,498,886 Circuit Module Redundancy Architecture
3 5,498,990 Reduced CMOS-Swing Clamping Circuit for Bus Lines
4 5,511,020 Pseudo-Nonvolatile Memory Incorporating Data Refresh Operation
5 5,576,554 Wafer-Scale Integrated Circuit Interconnect Structure Architecture
6 5,592,632 Defect Tolerant Integrated Circuit Subsystem for Communications between a Module and a Bus Controller
7 5,613,077 Method and Circuit for Communication between a Module and a Bus Controller in a Wafer-Scale IC System
8 5,615,169 Method and Structure for Controlling Internal Operations of a DRAM Array
9 5,655,113 Resynchronization Circuit for a Memory System and Method of Operating Same
10 5,666,480 Fault-Tolerant Hierarchical Bus System and Method of Operating Same
11 5,703,827 Method and Structure for Generating a Boosted Word Line Voltage and a Back Bias Voltage for a Memory Array
12 5,708,624 Method and Structure for Controlling Internal Operations of a DRAM array
13 5,729,152 Termination Circuit for Reduced Swing Signal Lines and Methods for Operating Same
14 5,737,587 Resynchronization Circuit for Circuit Module Architecture
15 5,784,705 Method and Structure for Performing Pipeline Burst Accesses in a Semiconductor Memory
16 5,787,267 Caching Method and Circuit for a Memory System with Circuit Module Architecture
17 5,790,138 Method and Structure for Improving Display Data Bandwidth in a UMA System
18 5,805,509 Method and Structure for Generating a Boosted Word Line Voltage and a Back Bias Voltage for a Memory Array
19 5,829,026 Method and Structure for Implementing a Cache Memory Using a DRAM Array
20 5,831,467 Termination Circuit with Power-Down Mode for Use in a Circuit Module Architecture
21 5,843,799 Circuit Module Redundancy Architecture Process
22 5,923,593 Multiport DRAM Cell and Memory System Using Same
23 5,940,088 Method and Structure for Data Traffic Reduction for Display Refresh
24 5,940,851 Method and Apparatus for DRAM Refresh Using Master, Slave and Self-Refresh Modes
25 5,999,474 Method and Apparatus for Complete Hiding of the Refresh of a Semiconductor Memory
26 6,000,007 Caching in a Multi-Processor Computer System
27 6,028,804 Method and Apparatus for 1T-SRAM Compatible Memory
28 6,075,720 Memory Cell for DRAM Embedded in Logic
29 6,075,740 Method and Apparatus for Increasing the Time Available for Refresh for 1T-SRAM Compatible Devices
30 6,078,547 Method and Structure for Controlling Operation of a DRAM Array
31 6,128,700 System Utilizing a DRAM Array as a Next Level Cache Memory and Method for Operating Same
32 6,147,535 Clock Phase Generator for Controlling Operations of a DRAM Array
33 6,147,914 On-chip Word Line Voltage Generation for DRAM Embedded in Logic Process
34 6,215,497 Method and Apparatus for Maximizing the Random Access Bandwidth of a Multi-Bank DRAM in a Computer
35 6,222,785 B1 Method and Apparatus for Refreshing A Semiconductor Memory Using Idle Memory Cycles
36 6,256,248 B1 Method and Apparatus for Increasing the Time Available for Internal Refresh for 1T-SRAM Compatible Devices
37 6,259,651 B1 Method for Generating a Clock Phase Signal for Controlling Operation of a DRAM Array
38 6,272,577 B1 Data Processing System with Master and Slave Devices and Assymetric Signal Swing Bus
39 6,295,593 B1 Method of Operating Memory Array with Write Buffers and Related Apparatus
40 6,324,110 B1 High-Speed Read-Write Circuitry for Semiconductor Memory
41 6,329,240 B1 Non-Volatile Memory Cell and Methods Of Fabricating and Operating Same
42 6,370,052 B1 Method and Structure of Ternary Cam Cell in Logic Process
43 6,370,073 B2 Single-Port Multi-Bank Memory System Having Read and Write Buffers and Method of Operating Same
44 6,393,504 B1 Dynamic Address Mapping and Redundancy in a Modular Memory Device
45 6,415,353 B1 Read/Write Buffers for Complete Hiding of the Refresh of a Semiconductor Memory and Method of Operating Same
46 6,425,046 B1 Method for Using a Latched Sense Amplifier in a Memory Module as a High-Speed Cache Memory
47 6,442,060 B1 High Density Ratio Independent Four Transistor RAM Cell Fabricated with a Conventional Logic Process
48 6,449,685 B1 Read/Write Buffers for Complete Hiding of the Refresh of a Semiconductor Memory and Method of Operating Same
49 6,457,108 B1 Method of Operating a System-on-a-Chip Including Entering a Standby State in a Non-Volatile Memory
50 6,468,855 B2 Reduced Topography DRAM Cell Fabricated Using a Modified Logic Process and Method for Operating Same
51 6,483,755 B2 Memory Module with High-Speed Latched Sense Amplifiers
52 6,496,437 B2 Method and Apparatus for Forcing Idle Cycles to Enable Refresh Operations in a Semiconductor Memory
53 6,504,780 B2 Method and Apparatus for Completely Hiding Refresh Operations in a DRAM Device Using Clock Division
54 6,509,595 B1 DRAM Cell Fabricated Using a Modified Logic Process and Method for Operating Same
55 6,510,492 B2 Apparatus for Controlling Data Transfer between a Bus and Memory Array and Method for Operating Same
56 6,512,691 B2 Non-Volatile Memory Embedded in a Conventional Logic Process
57 6,549,483 B2 RAM Having Dynamically Switchable Access Modes
58 6,573,548 B2 DRAM Cell Having a Capacitor Structure Fabricated Partially in a Cavity and Method for Operating Same
59 6,584,036 B2 SRAM Emulator
60 6,611,062 B2 Twisted Wordline Strapping Arrangement
61 6,642,098 B2 DRAM Cell Having a Capacitor Structure Fabricated Partially in a Cavity and Method for Operating Same
62 6,654,295 Reduced Topography DRAM Cell Fabricated Using a Modified Logic Process and Method for Operating Same
63 6,661,042 B2 One-Transistor Floating-Body DRAM Cell in Bulk CMOS Process with Electrically Isolated Charge Storage Unit
64 6,686,624 B2 Vertical One-Transistor Floating-Body DRAM Cell In Bulk CMOS Process With Electrically Isolated Charge Storage Region
65 6,707,743 B2 Method and Apparatus for Completely Hiding Refresh Operations in a DRAM Device Using Clock Division
66 6,714,470 B2 High Speed Read-Write Circuitry For Semi-Conductor Memory Device
67 6,717,864 B2 Latched Sense Amplifier As High Speed Memory In A Memory System
68 6,732,229 B1 Method And Apparatus For Memory Redundancy With No Critical Delay-Path
69 6,744,676 B2 DRAM Cell Having A Capacitor Fabricated Partially In A Cavity And Method For Operating Same
70 6,751,157 B2 Method and Apparatus for Completely Hiding Refresh Operations in a DRAM Device Using Clock Division
71 6,754,746 B1 Memory Array With Read/Write Methods
72 6,784,048 B2 Method Of Fabricating A DFRAM Cell Having a Thin Dielectric Storage Capacitor
73 6,795,364 B1 Method And Apparatus For Lengthening The Data-Retention Time Of A DRAM Device In Standby Mode
74 6,808,169 B2 Non-Volatile Memory With Crown Electrode To Increase Capacitance Between Control Gate and Floating Gate
75 6,841,821 B2 Non-Volatile Memory Cell Fabricated With Slight Modification to a Conventional Logic Process And Method of Operating Same
76 6,898,140 B2 Method and Apparatus for Temperature Adaptive Refresh in 1T-SRAM Compatible Memory Using Subthreshold Characteristics of MOSFET Transistors
77 6,913,964 B2 Method of Fabrication A Transistor Floating-Body DRAM Cell In a Bulk CMOS Process With Electrically Isolated Charge Storage Region
78 6,964,895 B2 Method of Fabricating Vertical One-Transistor Floating-Body DRAM Cell In Bulk CMOS Process with Electrically Isolated Charge Storage Region
79 7,051,264 B2 Error correcting memory and method of operating same